TRON Project Leader's Opinion

Ken Sakamura

Interfaculty Initiative in Information Studies, The University of Tokyo

The Field Programmable Gate Array (FPGA; a gate array that can be programmed on the spot) falls in the category of Programmable Logic Devices (PLDs; hardware logic devices that can be programmed), a type of semiconductor device, to which there is a history of over 30 years. In the middle of the 1970s, together with the problems I was trying to solve, I was researching a variable structure computer that could change its computing structure. As for the technique of changing the structure, it changed the instruction set matched to a problem using a microprogramming type computer. There, a Programmable Logic Array (PLA), which is a first generation PLD, was advocated, and although it was primitive, even manufactured products started to appear. The PLA drew a lot of attention as technology to advance microprogramming one step further, because, if a variable structure computer in which the logic circuits dynamically change by conforming to a problem can be realized, it is as if it has become a dream machine. However, although the PLA was very interesting in principle, what was realized were simple AND/OR combinations, and because the semiconductor density was low and the implementation technology was immature, in actuality it could not do much. At the time, because there was no product other than one in which we programmed after cutting the fuse, we could only program once, and it was not possible to dynamically make modifications. I proposed a Dynamic Logic Array (DLA) that could dynamically modify, but the technology for realizing it at the time did not catch up.

After that, quite some time elapsed, and then in the middle of the 1980s, the FPGA appeared. This is a device that is made in made in a manner in which a large number of logic blocks are arranged vertically and horizontally, and in which we program the wiring by means of built-in SRAM so that it is possible to dynamically realize arbitrary hardware logic circuits. At present, even products that can realize several million gates have appeared. The progress over these 30 years has been amazing. When I attempted to design a computer, at the beginning of the 1970s, there was nothing outside of putting together some of TI's TTL ICs for logic circuits, and then a little later bit slice microprocessors represented by the 6701 and 2901 appeared. The realization of the processor, sequencer, and the like was very easy, but the level of freedom was limited. That at present can be done using an FPGA, which can be used to develop your very own 32-bit CPU. For actual practice in research and schools, it is the most suitable. Even in product development, a system on a scale equivalent to several boards has been installed inside one chip. In developing system-on-a chip systems and systems in which we place ASICs on the periphery of general purpose CPUs also, we first create a prototype using an FPGA. Because the cost has been further lowered, from several years ago, we have embedded FPGAs into actual products, not prototypes, and in cases where a bug appears or a new function is added, instances of downloading and revising the hardware afterward are no longer rare.

By the way, when actually developing embedded systems with T-Engine, based on the idea that the hardware and the software must be developed as one, we have created and put into place an expansion board of the type that connects via T-Engine the general purpose microprocessor part and the user defined hardware logic part. I have advocated from before a technique in which hardware and software are simultaneously developed and then the debugged finished product is made into one chip. When we actually tried to do this, on T-Engine CPU boards, SH, ARM, MIPS, etc., for embedding had by and large been assembled, but there was the problem of how do we create an interface with the hardware logic, in other words, the FPGA side. At that point, last year, we quickly got the large maker Altera to participate, and they made public for us even the defined portion that connects to the chip's native bus. By means of this, we created a scheme in which the user developed logic part can be left as is, and in which one can use the defined logic without modification even when the CPU is changed. I greatly thank Altera for this. Then, as we moved into this year, it came about that even Xilinx, the largest maker in the PLD field, joined in the same scheme for us. On February 21, the Japanese local subsidiary made the announcement that "Xilinx will join the T-Engine Forum." In the PLD market, just Xilinix and Altera control 83 percent of the market (iSuppli survey, 2004), and thus the meaning of it having become possible to connect both leaders' products to T-Engine and T-Kernel is great.

I would like to confirm once again. T-Engine is a development board. The purpose of T-Engine and T-Kernel is to rapidly create specialized systems without regard to the CPU, and, moreover, to raise productivity through reutilization in a manner that allows for user created middleware and hardware modules to be freely passed around and used. This is the key concept of T-Engine, and together with the middleware distribution mechanism, the meaning of Altera and Xilinx positively lending their support is great. Along with thanking both companies for their initiatives to the T-Engine Forum, I am confident that T-Engine has drawn one step closer to the embedded development system industry standard of the future.

The above opinion piece by TRON Project Leader Ken Sakamura appeared on page 1 of Vol. 92 of TRONWARE. It was translated and loaded onto this page with the permission of Personal Media Corporation.

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Copyright © 2005 Sakamura Laboratory, University Museum, University of Tokyo