On November 15, the Embedded and Real-Time Systems Laboratory (Takada Laboratory) of Toyohashi University of Technology released to the public the µITRON4.0-specification freeware kernel TOPPERS/JSP. TOPPERS/JSP, which stands for "Toyohashi OPen Platform for Embedded Real-time Systems/Just Standard Profile," is a completely new reference implementation of a µITRON4.0-specification kernel mainly aimed at educational and research users with considerations for industrial users. Accordingly, it is not a revised version of ItIs, "ITRON Implementation by Sakamura Laboratory," a µITRON3.0-specification freeware kernel previously made available to the public via the Internet (click here).
According to a Japanese-language press release from the Takada Laboratory, the main features of TOPPERS/JSP are as follows:
The use of the TOPPERS/JSP by students, researchers, and/or companies is governed by the following licensing agreement, which is different from the GNU Public License that governs the use of the GNU/Linux operating system. In fact, it is closer to the license agreement governing the use of FreeBSD.
Copyright (C) 2000 by Embedded and Real-Time Systems Laboratory
The above copyright holder consents to the use, reproduction, alteration, and redistribution (hereafter called utilization) of this software (the following likewise includes alterations of this software) without compensation in cases limited to when the following conditions are satisfied.
(1) When this software is utilized as source code, the above copyright declaration, these conditions of utilization, and the following stipulation of no guarantee shall be included in its form as is in the source code.
(2) When this software is utilized in the form of binary code or in embedded form in machinery, one of the following conditions shall be satisfied.
(3) The above copyright holder shall be exempt from responsibility for whatever damages occur either directly or indirectly through the utilization of this software.
This software is something that is provided with no guarantee. The above copyright holder makes no guarantee whatsoever in regard to this software, including the possibility of its application. In addition, the above copyright holder shall also not bear responsibility for whatever damages occur either directly or indirectly through the utilization of this software.
As for future developments, the Takada Laboratory said it wants to raise the level of finish for the parts of the kernel where it is low, port the kernel to other processors and develop simulation environments for them, and broaden the applicability of the kernel in general. Perhaps most important to several people who have contacted TRON Web for further information on ITRON, the Takada Laboratory said it is planning to develop training materials for people planning to employ TOPPERS/JSP.
Those who would like to download the new µITRON4.0-specification kernel should go to: http://www.ertl.ics.tut.ac.jp/TOPPERS/.
* The Motorola 68040 and the Hitachi SH-3 are currently supported.
** In their press release, the Takada Laboratory wrote: "The task switching time in a typical case comes to approximately 2 µseconds on the SH-3 (SH7709; 80 MHz internal clock; 40 MHz external clock; 1 idle plus 2 wait cycle memory with the write-through cache ON). Also, the task control block size for each each task is 32 bytes (in addition, a stack region is necessary)." It should be noted here that the goal of the ITRON subproject is a task switching time of 1 µsecond, so this is pretty good performance.
TRON Project Leader Ken Sakamura gave a presentation on "Embedded Systems of the 21st Century and Their Technologies" on Wednesday, November 15, at the Microcomputer System & Tool Fair (MST2000), which was held at Tokyo International Exhibition Center (Tokyo Big Sight) from November 15 through 17. During his presentation, Prof. Sakamura talked about the rise of embedded Linux, commercially available embedded real-time operating systems (RTOSs), Windows CE 3.0, OSEK/VDW, and ITRON and JTRON. He also described the functionality and response times that a RTOS needs to be able to be able to serve as a platform for real-time applications. These are as follows:
As noted in the previous story, the µITRON4.0-specification kernel TOPPERS/JSP has achieved a task switching time of approximately 2 µseconds on the Hitachi SH-3, which is a microprocessor that is two generations old. Prof. Sakamura pointed out this fact--that ITRON's performance is on the order of µseconds, while other operating systems being proposed for consumer applications, such as embedded Linux and Windows CE, have a performance that is 10 times or more than this. Thus they are not really suited for embedded use.
In spite of its slow performance, embedded Linux has taken off in a big way outside of Japan, where ITRON is the standard for embedded systems. And, just like its desktop cousin, embedded Linux is on offer from multiple software houses. Just to name several, there are Lineo Inc.'s Embedix/Embedix RealTime, Monta Vista Software Inc.'s Hard Hat Linux*, Coollogic Inc.'s Coollinux, and LynuxWorks Inc.'s BlueCat Linux (originally, Lynx Real-Time Systems). Embedded Linux has already been selected for use in information appliances, hard disk video recorders, Internet terminals, dedicated Internet radios, cell-phones, and robots. Prof. Sakamura said what makes embedded Linux attractive to many developers is that there are no licensing fees, the source code is open, there is a tried and tested development environment, and there is abundant middleware for it. Another reason, of course, is that there are armies of programmers who have been trained to write Linux applications, so training costs are also marginal.
For those who are willing to pay licensing fees, there are well proven, commercially available RTOSs on the market, and they usually come with powerful development environments that were created expressly for writing real-time applications. The leading commercial RTOS for large-scale projects is Wind River Systems Inc.'s VxWorks. For small-scale applications, the most widely used commercial RTOSs are pSOS and VRTX. The former was developed by Integrated Systems Inc., and the latter was developed by Ready Systems Corporation. However, both of these companies have since disappeared. Integrated Systems was bought out by Wind River Systems in 1999, and Ready Systems was bought out by Microtec Research Inc., which in turn merged with Mentor Graphics Corporation in 1995. Users of commercial RTOSs thus have to deal with a dwindling number of suppliers, who can set prices to suit their revenue requirements. It is for that reason that most makers of consumer appliances, who cannot sell their products at high margins, are turning to freeware RTOSs.
One cannot mention operating systems for consumer appliances without mentioning Microsoft Corporation's Windows CE operating system**, and Prof. Sakamura took time out to describe its deficiencies, which are numerous. The biggest problem with Windows CE is that it requires considerable system resources to operate at acceptable speeds. In comparison to ITRON, which can run on a 10 MHz, 16-bit CPU with 64~128 KB of ROM and 1~4 KB of RAM, Windows CE--and, for that matter, even embedded Linux--requires at least a 100 MHz, 32-bit CPU with memory on the megabyte order. And even with resources on this level, Windows CE's performance is poor. For example, using a 166 MHz Pentium CPU, ISR processing (an interrupt processing routine corresponding to an interrupt handler) takes 10 µseconds, and IST processing (an interrupt processing thread) takes 100 µseconds. In spite of this sluggish performance, however, Microsoft announced Windows CE for Automotive version 3 in October. This version is intended for car navigation systems, electrical system control, and functions that raise safety in automobiles. However, a lot of major automobile manufacturers are not interested in it.
In Japan, ITRON, of course, is the standard RTOS used in the automobile industry, where its is used in demanding applications such as engine control. However, in Europe also there is a project like the TRON Project, the OSEK/VDW project, which has developed a RTOS expressly for the automotive industry called MotorWorks OSEK OS. Like the TRON Project on which is modeled, the OSEK/VDW project is a joint project between academia and industry, centering around the University of Karlsruhe. The largest automobile makers in Europe, such as BMW M GmbH and DaimlerChrysler AG are participating in this project. In fact, BMW has already incorporated the new operating system into one of its models. Like ITRON, MotorWorks OSEK OS is intended for hard real-time applications--such as engine, brake, and transmission control--in addition to less demanding applications such as car navigation systems. What the giant U.S. automobile industry will do now that both Japanese and European automobile makers are using high-performance, royalty free RTOSs will be interesting to see.
Prof. Sakamura saved the last part of his presentation for ITRON, of which he is rightly proud. After nearly two decades of hard work, µITRON has now become the leading RTOS for embedded applications worldwide. It is used in such common items as cell-phones, automobiles, high functionality facsimile machines, video cameras, and digital cameras. It has also been integrated into other operating systems, such as Windows NT/CE (Hitachi Ltd.'s DARMA), Linux (by US Software Corporation) and Windows CE (Elmic Systems Inc.'s Accel-µ), to speed them up. In addition, together with JTRON, ITRON has been selected for use in the next generation cell-phones, which are going to come into use in Japan in May 2001. As a result of this success, U.S. software firms have begun offering ITRON-compatible RTOSs. For example, there are: Red Hat Inc.'s eCos, which is an embedded RTOS with an ITRON compatibility layer; Accelerated Technology Inc. and Grape Systems Inc.'s jointly developed Nucleus µiPLUS; and US Software Corporation's TronTask!
As for embedded systems in the 21st century, Prof. Sakamura began by pointing out the current trends: the movement from PCs to non-PCs, embedded systems becoming highly functional and networkable, the appearance of information appliances and Internet appliances, and the development of environments with ubiquitous computers. These trends will continue and strengthen as we move into the 21st century. In addition, new trends have emerged. First, there is the emulation of hardware with software, as seen in the Transmeta Crusoe microprocessor, which emulates Intel x86 hardware. Emulation reduces the number of system parts, thus reducing system resources and power consumption, but the quality of the operating system becomes more important as this progresses. The second trend is the reduction of software into parts. This is particularly the case with middleware, such as the GUI and networking functions. These system software parts improve productivity while raising maintainability and reliability. They also make it possible to increase the functionality of systems, something that is very important in dynamic network environments.
Another trend that concerns the development and distribution of software parts is the trend toward open source code and open architectures. This is something that was pioneered in 1984 simultaneously by the TRON Project and the Free Software Foundation Inc., a non-profit organization in Boston, Massachusetts, which does fund raising for the GNU Project. By opening up source code and architectures, not only is reliability and productivity concerning software parts improved, but these parts also become common assets that serve as the infrastructure for the digital society of the future. Prof. Sakamura also discussed the "tuning of software parts" as a method to avoid irrational efforts to increase performance through hardware alone. By rewriting software parts at critical points for greater efficiency, demands for improved processing can be satisfied. The software parts to target for this tuning can be discovered by monitoring operational states and extracting instructions that appear with a high degree of frequency. In fact, if processor hardware is properly designed, it also could make use of this technique, thus allowing for the creation of a dynamic hardware architecture.
Prof. Sakamura, the designer of the world's first "total computer architecture," ended his presentation by discussing "total design." In total design, systems are first described as software based on modularized design concepts. The parts that should be incorporated as hardware are then described with a hardware description language (HDL). Once described with HDL, those parts can then be implemented using semiconductor technology. Total design is based on the idea that there has to be an appropriate division between software and hardware in order to meet the requirements of various applications so as to enable technological evolution. Although this design philosophy has come to the fore in the 20th century, it will only be in the 21st century that it is realized. Japan, as the birthplace of the TRON Project, is a leader in this field, and so Prof. Sakamura told his Japanese audience that the world is looking to Japan to show initiative. How true! If only Japan's leaders, both in business and government, realized that Japan has a leadership role to play in the world, both Japan and the world be better off.
* James Ready, the developer of VRTX, is said to be working on HardHat Linux. This is supposed to be a true embedded Linux operating system stripped of all the innards associated with a keyboard, a mouse, and a display.
** Microsoft also markets Windows NT Embedded for medium- and large-scale systems on an OEM basis. This operating system requires even greater system resources than Windows CE. In the area of memory, for example, it requires a minimum of 12 MB of main memory, and 8 MB of secondary memory.
The invention of the integrated circuit in the 1950s and the ensuing microelectronics revolution in the 1960s has led to a second industrial revolution in the latter half of the 20th century that has surpassed what even some science fiction writers had previously envisioned. The engine in this revolution has been the microprocessor, a tiny central processing unit on a chip, which was commercialized by Intel Corporation to meet the needs of a Japanese firm trying to fend off competition in the "calculator wars" that were taking place in Japan at the time. Since then many other companies have learned to make microprocessors, and the resulting competition has led to startling gains in computing performance without an increase in unit cost. The big question now is: what will come of the microelectronics revolution in the 21st century? In an attempt to answer that question, the TRON Association held a special seminar on Tuesday, November 28, at Gate City next to the JR Osaki Station in Tokyo to explain some developments that are on the way in the present decade.
The program began with an overview of the field of microelectronics by Prof. Ken Sakamura, the TRON Project Leader who was speaking in the capacity of editor-in-chief of IEEE Micro. Prof. Sakamura pointed out that the so-called Moore's Law of microprocessor development, i.e., that microprocessor speeds will double every 18-24 months, is still valid, but the question is for how long? According to this law, microprocessors in 2012 would be designed according to a .07 micron rule, they would run at a clock speed of 100 GHz, and they would be capable of processing 100 billion instructions per second (GIPS). However, it is expected that the manufacturing costs and technical hurdles involved in the creation of such high-speed microprocessors will prevent Moore's Law from be valid after 2010. Of course, that's not to say that microprocessor designers are not trying to figure out ways to increase the speed of microprocessors. They are, and Prof. Sakamura gave a detailed description of some of the technologies involved.
There are a variety of ways to speed up microprocessors. The easiest method is to raise the clock speed, but this has the drawbacks of creating heat and increasing power consumption, both of which create problems for designers of portable devices. Microprocessors with clock speeds of 2 GHz are being tested in research laboratories. The next most used method is to is design chips using schemes that process multiple instructions during a single clock cycle. Examples of such schemes are superscalar, super pipeline, Single Instruction stream Multiple Data stream (SIMD), Very Long Instruction Word (VLIW), and even the single-chip multiprocessor. The current favorite is VLIW, which is used by Intel Corp. for its 64-bit IA-64, Transmeta for its Crusoe, and Sun Microsystems Inc. for its Sun MACJ, but all of them present problems. Superscalar has problems with more than four instructions at a time, SIMD is useful only with multimedia instructions, VLIW requires a compiler that is difficult to write, and a single-chip multiprocessor requires a higher level system model to succeed.
And so what are computer system designers planning to do with microprocessors that process billions of instructions per second? The answer is to run artificial intelligence (AI) programs on them, Prof. Sakamura said. Using statistics developed by Dr. Hans Moravec*, Director of the Mobile Robot Lab at Carnegie-Mellon University, Prof. Sakamura said it is believed to require 50,000 million instruction per second (MIPS) to simulate one gram of nerve tissue in the human brain, and it would require 1 billion MIPS to simulate a human brain weighing 1,500 grams. Thus the demands of advanced AI applications are expected to pull microprocessor development forward for many more generations. In summing up his views about microprocessors in the 21st century, Prof. Sakamura said that more and more they will become software oriented, and that there will also be systems on a chip where hardware and software are co-designed. Low power microprocessor designs are also expected to be important (see below). However, at some time in the 21st century, Prof. Sakamura said that it will become impossible to improve the cost-performance of silicon-based systems.
After Prof. Sakamura spoke, four new microprocessors and/or microprocessor cores that have been developed by Japanese semiconductor firms--either alone or in conjunction with a foreign firm--were described. All of these microprocessors are aimed at low-cost, low-power consumer applications, in particular cell-phones and other wireless devices. This is where there is going to be tremendous growth in the future now that major markets, such as the U.S. market, have been saturated with personal computers and the "upgrade treadmill" has been broken by the appearance of the Internet.
|NEC Corporation MP98|
|Process technology||0.15 µm 5-layer-metal CMOS|
|Power supply||1.2~1.8 V (internal), 3.3 V (I/O)|
|Clock frequency||125 MHz (at 1.3 V)|
|Number of transistors||14 million|
|Die size||10.5 mm x 10.5 mm|
|Number of package pins||300 (signal) 500 (total)|
|Power consumption||1 W (at 1.3 V)|
|Performance||1 GIPS (at 1.3 V)|
|Data cache||64 KB (divided into 8 banks)|
|Instruction issue||2 issue (in order) x 4 multiprocessor|
|Data width||32 bit, 16 bit x 2 media data|
The first new microprocessor described was NEC Corporation's Merlot, which is the first MP98 architectural prototype. Mr. Edahiro Masato, who introduced the new microprocessor, began his discussion by talking about what the new chip is aimed at--artificial intelligence applications, especially voice recognition in portable terminals such as cell-phones. The chip will certainly have the performance to handle such an application. According to estimates from in-house simulation tools, on a 125 MHz clock, Merlot will be able to achieve 1 GIPS on a 1.3 volt power supply while consuming only 1 watt of electricity. So Merlot is a high-speed, low power microprocessor when running at top speed. Moreover, in order to further reduce power when full performance is not required or to set it to a bare minimum when in idle or sleep mode, Merlot is equipped with a Power Management Unit that switches off unneeded processing elements. This is an important feature to practicalize the portable terminals of the wireless Internet that is now coming into existence throughout the world.
The Merlot microprocessor is able to execute eight 32-bit (or 16-bit x 2) instructions in a single clock cycle. This is a result of the fact that four processor elements are integrated into a single chip using a multithreaded architecture. Each of these processor elements processes two two-way superscalar instructions simultaneously when the microprocessor is operating at maximum performance. All of these processor elements process in parallel when parallelism is extracted, and NEC has developed a special C compiler for the new microprocessor specifically for the purpose of extracting this parallelism from applications. In addition, in order to interact at high speed with the large dictionaries that have to be searched when running an artificial intelligence application such as a voice recognition system, Merlot is equipped with an on-chip two-channel, 64-bit SDRAM interface that has a throughput in excess of 1 gigabyte per second. The chip also has a 32-bit PCI bus interface, which is the standard for connecting personal computer peripherals.
For a detailed description of NEC's Merlot microprocessor, please see the article "A Single-Chip Microprocessor for Smart Terminals," which is on pages 12-20 the July/August 2000 issue of IEEE Micro.
|Process technology||0.15 µm copper interconnect|
|Clock frequency||400 MHz (at 1.5 V)|
|Die size (full core with FP)||14 mm x 14 mm|
|Die size (full core without FP)||11 mm x 11 mm|
|Power consumption||under 600 mW (core only)|
The second microprocessor described at the seminar was the Hitachi-STMicroelectronics** SH-5, which is actually the core of a microprocessor around which a system-on-chip (SoC) can be designed according to customer specifications. Mr. Kunio Uchiyama, who gave the presentation, pointed out that no single microprocessor can meet the needs of the wide range of multimedia platforms that is expected to come into existence in the 21st century. With the SH-5, Hitachi and its development partner have extended the widely used SuperH architecture to a 64-bit architecture, which has dramatically increased processing performance. Compared to the SH-4 which could do 230-360 MIPS depending on the version, the SH-5 core has a maximum processing speed of 714 Dhrystone v1.1 MIPS at 400 MHz while consuming 600 milliwatts of electricity. Some of the applications this microprocessor core is aimed at are: set-top boxes, digital television, voice-over-IP (VoIP) equipment, network processing, PDAs, Internet appliances, in-car information systems, and game machines
The SH-5 core is the fifth generation in the SuperH series, and so it has to be upwardly compatible with four previous generations of processors--of which 37 different versions were developed--while incorporating new technology to allow it to serve as the center of SoC designs. For that reason, the core is based on two operating modes, which are switched in and out by executing certain branch instructions. One mode is the SHcompact, which is based on the existing SuperH 16-bit instruction set that produces very compact code; and the other is the SHmedia, which is based on a new 32-bit instructions and SIMD instructions for multimedia and digital signal processing (DSP). Internally, the SH-5 core is based around a 1-issue, 64-bit superscalar architecture. There is a 64-bit multimedia unit (SIMD), and the core can also be equipped with an optional floating point unit (FPU) with a 128-bit vector graphics engine. There is also a memory management unit (MMU), on-chip debug support (SHdebug), 64 kilobytes of cache memory, plus an option for on-chip DRAM or flash memory.
For a detailed description of the Hitachi-STMicroelectronics SH-5 microprocessor core, please see the article "SH-5: The 64-Bit SuperH Architecture," which is on pages 28-38 the July/August 2000 issue of IEEE Micro.
|Process technology||0.18 µm 5-metal-layer CMOS|
|Power supply||1.8 V|
|Clock frequency||266 MHz|
|Number of transistors||6.7 million|
|Die size||7.5 mm x 7.5 mm|
|Power consumption||2 W, core 1.5 W (at 1.8 V)|
|Cache||16 KB x 2 (instruction + data)|
|Bus interface||SDRAM, system (both 133 MHz)|
Mr. Atsuhiro Suga described the third microprocessor at the seminar, Fujitsu's FR500, which is the core for a new line of processors based on an independently developed VLIW architecture. This new line is called the Fujitsu RISC-VLIW, or FR-V, family, and it is aimed at the same advanced embedded consumer applications that the other processors described at the seminar are aimed at. In order to meet the same cost-performance and power consumption requirements, Fujitsu reasoned that a VLIW-based architecture would be best. The advantage of a VLIW architecture is that the compiler rather than hardware on the processor itself--which is the case with a traditional superscalar architecture--is responsible for determining whether multiple instructions can be processed in parallel. Accordingly, by monitoring the execution of compiled code and then recompiling the parts with a high execution count for better execution, it is possible to improve the performance of the processor. The drawback, of course, is that hardware performance and/or sales will ultimately depend on the quality of the compiler and other software tools used for application software development.
In comparison to other VLIW processors developed for advanced media applications, which use an eight-way VLIW architecture, Fujitsu's FR500 uses a four-way VLIW architecture, which makes the processor's die size smaller. This four-way VLIW architecture issues up to four instructions, each of which is 32 bits long, simultaneously in a 128-bit-wide VLIW packet. The instruction set is made up of integer, floating point, and media instructions for global scheduling, and there are two execution units for each of these on the processor. The VLIW format used for parallel execution is of variable length, and all instructions use a packing flag to demarcate the VLIW boundary. This is done to suppress NOPs, or "No Operations," which are empty operations to fill out a VLIW when a real instruction cannot be found for execution. NOPs reduce processing performance and increase memory size, both big drawbacks in an embedded processor. Another drawback in a processor for embedded design is high power consumption. Since the FR500 is power hungry in comparison to its competition, Fujitsu is offering another lower power core, the FR300, to developers of portable devices.
For a detailed description of Fujitsu's FR500 microprocessor, please see the article "Introducing the FR-500 Embedded Microprocessor," which is on pages 21-27 the July/August 2000 issue of IEEE Micro.
|Process technology||0.18 µm CMOS|
|Clock frequency||72 MHz|
|Power supply||1.8 V|
|Power consumption (typical)||0.2 mA/MHz (current)|
The only speaker to mention the price of the advanced microprocessors described at the seminar was Mr. Toyohiko Yoshida of Mitsubishi Electric Corporation, who spoke about the D10V media processor core that has been optimized for very low power applications, such as cell-phones. Unlike Intel Corporation, which can get hundreds of dollars for one of its latest processors, media processors based on the D10V core have to be priced at 3,000 yen or less for the Japanese market. This may sound like good news for Intel and bad news for Mitsubishi Electric, but personal computer sales are starting to slow, and non-PC devices are starting to replace them, so the future is bright for companies that can do low power, high-performance processors. On top of that, Intel is being challenged by semiconductor makers who make clones of its x86 flagship line. Advanced Micro Devices Inc. is challenging Intel for the fastest chip, while other companies such as Transmeta Corporation and National Semiconductor Corporation are offering low power alternatives for portable PCs. Accordingly, as PC sales slow and the wireless Internet develops, Intel's fortunes are highly likely to change.
Mitsubishi Electric's D10V is based on a dual issue RISC architecture optimized for low power that combines the architectures of a microcontroller unit and a digital signal processor (DSP), and which features unified RAM in a simplified architecture for higher programmability. The D10V uses a 2-way VLIW of 32-bit fixed length, 16 16-bit general registers, two 40-bit accumulators, and a data memory access interface that is 32 bits wide. This unified data memory allows for an increase in programmability without the use of dual-port RAM. According to the results of several benchmark tests carried out by Mitsubishi Electric, the D10V is able to achieve signal throughput on a par with or in excess of conventional DSPs, while maintaining the flexibility to serve as a processor for general purpose applications. Creating programs for the D10V is also fairly easy, since the worldwide, de facto standard GNU tools are used on a widely available host, either a Sun Microsystems Inc. workstation or an IBM-PC/AT-compatible personal computer running either MS Windows NT or MS Windows 95. User support is available through the Internet from Cygnus Solutions, which was bought out by Red Hat Inc.
|IEEE 802.11b||Bluetooth Ver. 1|
|Speed||11 Mbps maximum||432.6 Kbps full duplex|
|No. of connections||1 to many (up to 128)||1 to many (up to 7)|
|Connection setting||Required beforehand||
|Use||Data transfer||Voice, data transfer|
|Standard type||World standard||World standard|
All the microprocessors described above are aimed primarily at portable applications, in particular the ubiquitous cell-phone. For that reason, the seminar also included two presentations on auxiliary technologies that are essential for the realization of practical portable devices in the 21st century. The first of these was on Bluetooth wireless interconnection technology, which was given by Mr. Yoichi Takehashi of Toshiba Corporation and included a demonstration of an MPEG4 video transmission at approximately 400 Kbps. At this speed, a display rate of 15 frames per second was achieved with no data loss while a camera wielding assistant wandered around the conference room and filmed the audience. The output was displayed at the front of the room on a projector screen for all to see. It immediately became clear to the members of the seminar audience that Bluetooth technology holds a lot of promise, the big question is--will everything go according to plan? Bluetooth is essentially "wireless plug and play" on the grandest scale possible--across all types of computerized equipment regardless of operating system and/or manufacturer. (Click here for a detailed discussion of Bluetooth issues.)
Bluetooth, which is named after a 10th century Viking king who lived in what is now Denmark, is a royalty free, open standard that was originally promoted by five companies--Ericsson, Nokia, Intel, IBM, and Toshiba--beginning in 1998. Today, more than 1,800 companies are participating in the Bluetooth Special Interest Group (SIG). Version 1.0 utilizes 78 MHz of universally available bandwidth between 2.402 GHz and 2.480 GHz at an output of 1 milliwatt, which is effective for a radius of 10 meters. Throughput is 64 Kbps (synchronous) for voice, and 432.6 Kbps (full duplex) or 721.56 Kbps (asymmetric) for data, although this throughput will be increased to between 2 Mbps and 12 Mbps in the same waveband with Version 2. In order to ensure that each maker implements the Bluetooth middleware specifications in like manner, the Bluetooth project, like the TRON Project's ITRON subproject, has introduced "profiles." Each manufacturer is required to specify which profile a particular piece of equipment complies with, and users will be able quickly determine which profile is supported. The profiles that have been drawn up to date mainly deal with mobile telephony and personal computer connectivity, but working groups are currently at work on profiles for a much broader range of applications.
|Sony Corp. Memory Stick|
|Number of pins||10|
|Terminal shape||1 row of flat electrodes|
|Transfer (read) speed||2.5 MBps maximum|
|Capacity||4 MB~128 MB|
|Write unit||512 B|
|Erase unit||8 KB or 16 KB|
|Power source voltage||2.7 V~3.6 V|
|Outer dimensions||21.5 mm x 50 mm x 2.8 mm (width x length x thickness)|
The second auxiliary technology presented at the seminar was the Memory Stick, which was described by Mr. Shigeo Araki of Sony Corporation. The Memory Stick is a pretty simple thing. In essence, it is a flash memory--an Electrically Erasable Programmable Read-Only Memory (EEPROM) onto which data can be rewritten over 100,000 times--that provides the secondary memory storage capabilities normally associated with a hard disk drive or a compact disc drive. Memory Sticks come in two versions: those with copyright protection, and those without it. Memory Sticks with copyright protection have MagicGate technology, which is used to protect the contents of copyrighted data and to authenticate whether a device legally supports Memory Stick. These are called "MagicGate Memory Sticks," and they come in 32- and 64-megabyte capacities at present. There is also a half-size Memory Stick in the works for very small-scale equipment called "Memory Stick Duo." The largest capacity Memory Sticks currently available have a capacity of 128 megabytes, but 256-megabyte and 1-gigabyte versions of Memory Stock will become available in FY 2002 and FY 2003, respectively.
Although Memory Stick technology was developed and patented by Sony Corporation, the company licenses the technology to other companies. In addition to Sony, Memory Stick products are manufactured by Fujitsu Ltd., I/O Data Device Inc., and Lexer Media Inc. Together, these manufacturers are expected to put out 10 million Memory Stick products in FY 2000, 20 million in FY 2001, 40 million in FY 2002, and 60 million in FY 2003. The most popular uses for Memory Stick at present are digital photography, portable music players and voice recorders, and portable computing devices. However, the range of applications is expected to expand markedly in the future. Memory Stick is planned for use with third-generation wireless telephony devices, home entertainment and car navigation systems, and even Sony's Aibo robot dog. Memory Stock Duo is aimed at wearable applications, such as wristwatches. In order to make Memory Stick compatible with high-performance devices, Sony is planning to increase the data transfer rate--the read speed--from the current 2.5 megabytes per second to 20 megabytes per second.
For a detailed description of Sony's Memory Stick, please see the article "The Memory Stick," which is on pages 40-46 the July/August 2000 issue of IEEE Micro.
* Readers unfamiliar with Dr. Moravec's work might be surprised to learn that his ultimate goal is to create by 2050 humanoid robots ("mind children") into which humans can download their intelligence and/or consciousness, thus allowing for human descendants to evolve faster while becoming near immortals. Some people, such as Sun Microsystems Inc.'s Bill Joy who has written a book warning about dangers of advanced technology, are horrified by this type of research. However, there are probably others who would find the results interesting, if for no other reason than they would allow Intel Corporation to recycle its branding mark at mid century--from 'Intel Inside' to 'Inside Intel'.
** STMicroelectronics is a company formed from Thomson Semiconducteurs of France and SGS Microelettronica of Italy in 1987.